The present invention relates to interconnection structures and methods for forming the structures.
To meet recent increase in the speed and integration density of electronic devices such as semiconductor devices, copper (Cu) having low resistance has been more frequently used as an interconnect material.
FIG. 19B is a cross-sectional view showing an example of a conventional multilevel interconnection structure formed by using Cu. As shown in FIG. 19B, a first interconnect 2 is buried in an insulating film 1 formed on a semiconductor substrate (not shown), and a SiN film 3, a SiO2 film 4 and a FSG (fluorine-doped silicate glass, i.e., fluorine-doped silicon oxide) film 5 are formed in this order over the insulating film 1 and the first interconnect 2. A via hole 6 is formed through the SiO2 film 4 and the SiN film 3 to reach the first interconnect 2. An interconnect trench 7 is formed in the FSG film 5 to reach the via hole 6. A barrier film 8 and a Cu film 9 are buried in this order in the via hole 6 and the interconnect trench 7, thereby forming a via 10 and a second interconnect 11 in the via hole 6 and the interconnect trench 7, respectively. A SiN film 12 is formed on the FSG film 5 and the second interconnect 11.
As shown in FIG. 19B, the first interconnect 2 and the second interconnect 11 are electrically connected to each other by way of the via 10. Each of the first interconnect 2 and the second interconnect 11 is electrically connected to another element (now shown) or an external electrode (not shown.) In this manner, the first interconnect 2, the via 10 and the second interconnect 11 constitute part of a closed circuit in actual use.
FIG. 19C is a plan view showing the multilevel interconnection structure shown in FIG. 19B when viewed above. As shown in FIG. 19C, the first interconnect 2 has a width smaller than that of the second interconnect 11. Specifically, the width of the first interconnect 2 is 0.2 μm, the diameter of the via 10 (the via hole 6) is 0.20 μm, and the width of the second interconnect 11 is 10 μm.
FIGS. 18A through 18C and 19A are cross-sectional views showing respective process steps of a conventional method for forming the multilevel interconnection structure shown in FIG. 19B (see Japanese Unexamined Patent Publication (Kokai) No. 2000-331991.)
First, as shown in FIG. 18A, an insulating film 1 is formed on the surface of a semiconductor substrate (not shown), and then a first interconnect 2 is formed in the insulating film 1.
Next, as shown in FIG. 18B, a SiN film 3, a SiO2 film 4 and a FSG film 5 are formed in this order over the insulating film 1 and the first interconnect 2 by a plasma chemical vapor deposition (plasma CVD) process. Thereafter, lithography and dry etching are alternately performed twice (i.e., lithography and dry etching are each performed twice), thereby forming a via hole 6 through the SiO2 film 4 and the SiN film 3 to reach the first interconnect 2 and also forming an interconnect trench 7 in the FSG film 5 to reach the via hole 6.
Then, as shown in FIG. 18C, a barrier film 8 is deposited by a physical vapor deposition (PVD) process to fill the via hole 6 and the interconnect trench 7. Then, a Cu film 9 is formed by a plating process on the barrier film 8 to completely fill the via hole 6 and the interconnect trench 7.
Thereafter, as shown in FIG. 19A, parts of the barrier film 8 and the Cu film 9 extending off the interconnect trench 7 are removed by a chemical/mechanical polishing (CMP) process. In this manner, a second interconnect 11 is formed in the interconnect trench 7, and a via 10 connecting the first interconnect 2 and the second interconnect 11 to each other is formed in the via hole 6.
Lastly, a SiN film 12 is deposited over the FSG film 5 and the second interconnect 11 (the Cu film 9), thus completing the multilevel interconnection structure shown in FIG. 19B.